The present invention relates to a system for the detection of programmable stop codes in a data transfer between the memory of a microprocessor and peripheral equipment in a processor assembly utilizing a direct access circuit to the memory.
This invention relates to the management of the data exchanges in a processor assembly incorporating a microprocessor, peripheral equipment and a direct access circuit to the microprocessor memory.
It is known that direct access circuits to the memory of a microprocessor are widely used in processor assemblies. They make it possible to more easily manage data exchanges between the memory of a microprocessor and its peripheral equipment. They also make it possible to increase the speed of the data exchanges. However, existing direct access circuits or DAC's only permit programming on a byte code and not a stop code. This leads to a significant time loss, which is prejudicial. The detection of a programmable stop code makes it possible to obviate this disadvantage.
It is also known that in data transmission it is always possible to forecast the number of characters to be transmitted. However, a problem occurs on reception of said data, where three different types of solution can be envisaged:
not to manage the reception with the aid of a DAC; PA1 to supervise the reception by a timing system; PA1 to introduce a stop code detection system, which is either unique, or non-programmable.
However, these different solutions have serious disadvantages.
In the case where reception is managed by a microprocessor and not a direct access circuit, the data exchange or transfer speeds are not very high, particularly if the microprocessor simultaneously has to manage several transfer lines.
When the reception is supervised by a timing system, the latter is dependent on the asynchronous line speed and must be modifiable. This solution can only be validly used, when the data transfer takes place in a "block" mode. In this case, the detection of the end of an exchange or transfer takes place much later than the true end of said exchange. For example, at a transmission speed of 300 bauds, the transfer of a character lasts 33 ms. Thus, the timing system is regulated so as to detect the fact that no character has been received for more than 40 ms. Thus, the time lag between detection and the effective end of an exchange is 40 ms.
The solution consisting of using a stop code detection system, which is either unique, or non-programmable is not very satisfactory. When it is necessary to detect a stop code, the simplest procedure is to detect a single character, fixed once and for all. However, a single stop character is not always adequate, and it is often necessary to have the possibility of modifying this character. In general, in known systems, the detection of a programmable stop code takes place by means of a register and a comparator. If it is then wished to have several different stop codes for the same data exchange (which is often the case), it is necessary to increase the number of registers and consequently the equipment making it possible to program these registers and detect the end of an exchange is made heavier, which is very onerous. In known systems, using a register and a comparator for each stop code, it is necessary, when it is wished to detect n simultaneous stop codes, to use n stop codes storage registers having n different inputs and consequently requiring n different address decodings. It is also necessary to use n comparators comparing the content of the registers with the data present on the bus. It is also possible to use only a single comparator for carrying out the comparison with the content of n registers, but in this case, it is necessary to present the content of n registers successively on one of the comparator inputs. Thus, in this case, n non-contiguous signals of a spectrum must be supplied for validating the output of n registers. These signals can be processed from one or more delay lines or a shift register, controlled at a given frequency. Although this solution reduces the number of comparators necessary, it considerably complicates the system control logics.